Key Takeaways

- IBM's new 0.7nm 'nanostack' design stacks transistors vertically, packing 100 billion onto a fingernail-sized chip
- The technology delivers up to 50% higher performance or 70% greater energy efficiency versus IBM's 2021 2nm chips
- Commercial production remains five years away, with no manufacturing partner announced yet
IBM announced what it claims is the world's first chip technology capable of producing transistors smaller than one nanometer. The 0.7nm architecture, which the company calls "nanostack," stacks transistors vertically rather than laying them flat. IBM says the design packs roughly 100 billion transistors onto a fingernail-sized surface, about twice the density of its 2nm chip from 2021.
Shares rose over 6% in premarket trading on the news, though gains settled to about 1.9%. The stock has fallen roughly 11% year-to-date.
What does the nanostack architecture actually do?
Traditional chip designs spread transistors horizontally across a surface. IBM's nanostack flips this approach, stacking components in three dimensions. The result, according to IBM: up to 50% higher performance or 70% greater energy efficiency compared to its previous generation.
"With our new nanostack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency," said Jay Gambetta, director of IBM Research.
Beyond raw compute, IBM claims the technology shrinks SRAM memory circuits by 40%. That matters for AI workloads. Nvidia's Groq chips and Cerebras Systems' processors both rely heavily on SRAM for fast on-chip memory. Both currently depend on TSMC for manufacturing.
How does this compare to Intel and TSMC?
The timing is pointed. Last week, Intel announced that its 18A process, which produces 1.8nm chips, entered risk production. That's the testing phase before commercial manufacturing. TSMC, the world's largest contract chipmaker, has been ramping 3nm production and working toward 2nm.
IBM's 0.7nm announcement leapfrogs both, at least on paper. But there's an important caveat: IBM says production could begin within five years. Intel and TSMC are shipping advanced chips now.
IBM also hasn't named a manufacturing partner for this technology. The company has previously licensed chip designs to Samsung and Japan's Rapidus. Whether either will produce the nanostack architecture remains unclear.
Why this matters for Moore's Law
Moore's Law, the observation that transistor density doubles roughly every two years, has guided semiconductor development for six decades. But physics has been closing in. At 1nm, you're dealing with features just a few atoms wide. Quantum effects become harder to manage. Heat becomes harder to dissipate.
Vertical stacking offers a path forward. Instead of fighting to shrink transistors further on a flat plane, chipmakers can build upward. It's the same principle that let cities grow by adding floors rather than expanding their footprint.
For AI, the implications are significant. Large language models and other neural networks demand massive parallel processing. More transistors means more compute in the same power envelope. A 70% efficiency gain, if it holds in production, would let data centers run larger models without proportionally larger electricity bills.
The five-year gap is the real question
IBM has a history of announcing breakthrough chip technology years before commercial availability. Its 2nm process, unveiled in 2021, still hasn't reached mass production. Samsung has licensed the technology but hasn't shipped 2nm chips at scale.
Five years is a long time in semiconductors. TSMC and Intel will iterate multiple times before IBM's nanostack reaches fabs. The technology's real impact depends on whether IBM can close that gap, and whether it can find a manufacturing partner willing to bet on a fundamentally different transistor architecture.
Logicity's Take
IBM's announcement is technically impressive but commercially uncertain. The company excels at research breakthroughs but has struggled to translate them into competitive products since exiting chip manufacturing in 2014. TSMC and Samsung will be watching closely, but neither has committed to this architecture. For enterprises planning AI infrastructure, the practical takeaway is that meaningful density gains from vertical stacking are coming, but not before the 2030 timeframe. Plan your current workloads around what TSMC and Nvidia are shipping now, not what IBM might license in half a decade.
Frequently Asked Questions
What is IBM's nanostack architecture?
Nanostack is IBM's new transistor design that stacks components vertically in three dimensions rather than spreading them horizontally. This allows more transistors to fit in the same physical space.
When will IBM's sub-1nm chips be available?
IBM estimates commercial production could begin within five years, placing availability around 2030 at the earliest.
Who will manufacture IBM's new chips?
IBM hasn't announced a manufacturing partner. The company has previously licensed chip technology to Samsung and Japan's Rapidus.
How does 0.7nm compare to current chip technology?
Intel's newest process produces 1.8nm chips, and TSMC is ramping 3nm production while working toward 2nm. IBM's 0.7nm would be significantly smaller than any commercially available technology.
Why does transistor size matter for AI?
Smaller transistors allow more compute power in the same space with better energy efficiency. AI workloads require massive parallel processing, so higher transistor density enables larger models without proportionally higher power consumption.
Deep technical background on IBM's vertical transistor approach
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Source: Tech-Economic Times / ET
Manaal Khan
Tech & Innovation Writer
Produced with AI assistance and reviewed by the Logicity editorial team. Learn more in our Editorial Policy.
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