Huawei Claims 1.4nm-Class Chips by 2031 Without EUV

Key Takeaways

• Huawei claims its LogicFolding architecture delivers 55% higher transistor density and 41% better power efficiency without EUV lithography
• The company has secretly mass-produced 381 chip designs using this methodology over six years
• First commercial LogicFolding chips arrive this autumn in Kirin processors for the Mate 90 series

Huawei has announced a chip design framework it claims can match global semiconductor leaders without access to advanced Western manufacturing equipment. The company targets '1.4nm-class' transistor performance by 2031 through pure architectural innovation.

He Tingbo, Huawei board member and president of its semiconductor division HiSilicon, unveiled the approach at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai on Monday. The announcement included two major components: a new 'Tau Scaling Law' to replace Moore's Law, and a 'LogicFolding' architecture built on that principle.

“We are shifting the focus from geometric shrinking to time-domain efficiency, treating the signal propagation delay as the primary variable for future scaling.”

— He Tingbo, President of HiSilicon

What LogicFolding Actually Does

Traditional chipmaking follows Moore's Law: shrink transistors physically to pack more onto a chip. This requires extreme ultraviolet (EUV) lithography machines at advanced nodes. US sanctions have blocked Chinese firms from buying these machines, leaving companies like Huawei stuck at older process nodes.

Huawei's answer is to change what it optimizes for. Instead of shrinking transistors geometrically, the Tau Scaling Law focuses on signal speed. It measures how fast data moves across a system rather than how small components are.

LogicFolding executes this theory commercially by physically folding and stacking logic circuits into a dual-layer framework. By shortening internal wiring, Huawei claims the design eliminates signal delay while achieving density improvements that would normally require smaller transistors.

The Claimed Performance Numbers

Huawei's presentation included specific performance claims for LogicFolding:

• 55% increase in transistor density compared to conventional designs at the same process node
• 41% improvement in power efficiency
• 12.7% boost in clock frequency for upcoming Kirin chips
• 1.4nm-class equivalent density by 2031 without EUV equipment

The company said it has refined this methodology over six years, quietly designing and mass-producing 381 chips based on the principle before going public.

Commercial Rollout Timeline

Huawei plans to debut LogicFolding in flagship Kirin smartphone processors this autumn. These chips will power the anticipated Huawei Mate 90 series.

The roadmap extends beyond phones. By 2030, Huawei aims to scale this architecture to its Ascend AI processors and data center clusters. The company frames this as providing local alternatives to restricted Nvidia hardware. By 2031, Huawei projects it can design chips with transistor density equivalent to 1.4nm-class nodes.

Skepticism and Technical Questions

Online discussion of Huawei's claims is split. On forums like r/hardware and Hacker News, skeptics argue that architectural tricks cannot overcome fundamental physics. Heat dissipation and leakage current are problems that smaller transistors solve. No amount of circuit folding changes how much heat a given transistor generates or how much current leaks through it.

Others point to Huawei's track record. The company has repeatedly delivered competitive chips under heavy sanctions, including the Kirin 9000S that surprised analysts in 2023. Engineering workarounds that seemed impossible have materialized before.

The truth likely sits somewhere in between. LogicFolding may deliver real improvements at the architectural level while still facing hard physical limits that geometric scaling addresses. Whether those improvements add up to '1.4nm-class' performance depends on how Huawei defines that equivalence.

What This Means for the Chip Industry

If LogicFolding delivers even half of its claimed benefits, it represents a significant shift in how semiconductor competition works. US sanctions assumed that blocking equipment access would freeze Chinese chip development at older nodes. Huawei is now arguing that equipment access is not the only path forward.

This has implications beyond Huawei. Other Chinese firms watching this announcement may pursue similar architectural approaches. Western chipmakers may need to accelerate their own 3D stacking and advanced packaging work to maintain their lead.

The first real test comes this autumn when Kirin chips based on LogicFolding reach consumers. Independent benchmarks will reveal whether the architecture delivers its promised density and efficiency gains in practice.

Frequently Asked Questions

What is Huawei's LogicFolding architecture?

LogicFolding is a chip design approach that physically folds and stacks logic circuits into a dual-layer framework. It shortens internal wiring to reduce signal delay, claiming 55% higher transistor density without requiring advanced EUV lithography equipment.

What is the Tau Scaling Law?

Tau Scaling Law is Huawei's proposed replacement for Moore's Law. Instead of measuring progress by transistor size, it focuses on signal propagation delay, optimizing how fast data moves across a chip rather than how small components are.

When will LogicFolding chips be available?

Huawei plans to launch Kirin processors with LogicFolding architecture this autumn in the Mate 90 smartphone series. Ascend AI processors using the technology are targeted for 2030.

Can LogicFolding really bypass EUV restrictions?

Huawei claims the architecture achieves density improvements normally requiring smaller process nodes. Skeptics note that fundamental physics problems like heat dissipation still exist. Real-world performance will be tested when products launch.

How many chips has Huawei made with this technology?

According to He Tingbo's presentation, Huawei has mass-produced 381 different chip designs using this methodology over six years of development before the public announcement.

Source: Latest from Tom's Hardware