Cadence Design Systems raised its full-year 2026 revenue forecast to between $6.26 billion and $6.34 billion, up from its prior range of $6.13 billion to $6.23 billion. The EDA software maker cited strong demand from chipmakers building AI accelerators and complex systems-on-chip. Shares jumped more than 5% in extended trading on July 28.
The revised guidance tops Wall Street's consensus estimate of $6.21 billion. Cadence also bumped its adjusted profit outlook to $8.05-$8.15 per share, above the previous $7.85-$7.95 range and analyst estimates of $7.96.
What's driving the forecast bump?
How AI is Changing Chip Design | Insights from Cadence Engineers
Cadence sells electronic design automation tools, the software that engineers use to design and validate semiconductors and electronic systems. Its customer list includes Nvidia and Apple. Both are racing to ship more capable AI chips, and that race translates directly into demand for Cadence's design software.
Second-quarter revenue rose 24.2% year-over-year to $1.584 billion, roughly in line with estimates. Adjusted profit hit $2.11 per share versus expectations of $2.05. The numbers suggest Cadence is not merely riding AI hype but converting that interest into bookings.
AuraStack: Cadence's new AI agent
Earlier in July, Cadence launched AuraStack, an AI "super agent" that lets engineers describe chip design goals in plain language. AuraStack then plans and executes tasks using Cadence's existing EDA tools, laying out circuits and running virtual tests without manual orchestration.
The product matters because chip design is slow. A typical SoC project can run 18 to 36 months from architecture to tapeout, with much of that time spent iterating layouts and verifying timing. If AuraStack compresses even a fraction of that cycle, the productivity gain is substantial.
Cadence has not disclosed AuraStack pricing or licensing terms. Competitors Synopsys and Siemens EDA are building similar AI-assisted flows. The EDA market is a duopoly-plus-one, so any tooling advantage tends to be temporary.
What it means for the chip supply chain
Cadence's backlog figure, $8.1 billion at quarter-end, signals that customers are locking in multi-year software commitments. That backlog visibility gives the company confidence to raise guidance even as the broader semiconductor market debates cyclical peaks.
For CTOs and engineering leads at chip startups, the implication is clear: design software costs are rising alongside AI compute costs. Cadence's pricing power tracks the complexity of the chips its customers want to build. As transistor counts climb and AI workloads demand custom silicon, EDA budgets will follow.
Logicity's Take
Cadence's raised forecast is less about one good quarter and more about where AI chip investment is headed. Hyperscalers and consumer electronics giants are all designing custom accelerators, and every one of those projects funnels money to Cadence or Synopsys. AuraStack is a hedge: if AI compresses design cycles, Cadence wants to own the tool that does it, not be disrupted by it. Watch whether customers report actual tapeout-time reductions. That will determine if AuraStack is a feature or a business.
Another chip design startup raising capital, illustrating broader semiconductor investment trends
What Cadence didn't say
The company did not break out how much of its revenue comes from AI-specific design work versus traditional digital, analog, or verification tools. It also did not disclose AuraStack adoption metrics or revenue contribution. Those details will matter as investors try to separate AI tailwind from core business growth.
The 24% quarterly revenue growth is impressive, but Cadence's forward guidance implies growth decelerating into the back half of the year. Whether that reflects conservatism or a cooling order book remains to be seen.
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Source: Tech-Economic Times / ET
Huma Shazia
Senior AI & Tech Writer
Produced with AI assistance and reviewed by the Logicity editorial team. Learn more in our Editorial Policy.
